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By KrDe
Submitted: May 12 2013 / 02:51

Advances in technologies are driving integration of more features and higher performance into smaller chip designs that are resulting in increasing power and thermal density and design complexity. Mobile computing devices require higher performance with more battery life while the need for higher performance servers places more demands on data center–server efficiency due to rising costs of energy, operation, and infrastructure. Holistic dynamic thermal and power management explicitly couples thermal and power management from the chips to computer to server and to the data center. Additional challenges are placed on hardware and software development and validation time as design complexity and density increase. A common architecture for power and thermal management facilitates more efficient hardware and software development, validation, and reuse across segments. This article proposes a common memory open and closed loop thermal management (OLTM, CLTM) integrated thermal and power capping with a technique called running average power limiting (RAPL) architecture. These traditional power and thermal features are described as part of an autonomic framework for power and thermal management integrated with advanced interrupts/signaling and power limiting (RAPL) concepts. We introduced efficient RAPL that enforces power limits over a sliding time widow, while minimizing performance impact in highly dynamic and transient data center workloads. We also introduce the concept of a standard software interface through standard configuration architecture (SCA) that produces a uniform telemetry and event signaling infrastructure across client and server segments. We also introduce the design considerations for a data center management data aggregation and workload autonomics framework that can make use of power, thermal, and throughput constraints to influence reduction of maintenance costs, to drive greater efficiencies for more flexibility, and to dynamically scale resource pools.
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