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Load Register

07.01.2011
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        // Load register

library ieee;
use ieee.std_logic_1164.all;

entity loadRegister is
	port(
		q	: in std_logic_vector(2 downto 0);
		load	: in std_logic;
		clk	: in std_logic;
		y	: out std_logic_vector(2 downto 0);
		clrn	: in std_logic;
		prn	: in std_logic
	);
end loadRegister;

architecture main of loadRegister is
	signal m, q: std_logic_vector(2 downto 0);

	component mux
		port(
			a: in std_logic;
			b: in std_logic;
			s: in std_logic;
			z: out std_logic
		);
	end component;

	component dff
		port(
			d	: in std_logic;
			clk	: in std_logic;
			clrn	: in std_logic;
			prn 	: in std_logic;
			q	: out std_logic
		);
	end component;
begin
	w1: mux port map( q(0), i(0), load, m(0) );
	w2: mux port map( q(1), i(1), load, m(1) );
	w3: mux port map( q(2), i(2), load, m(2) );

	w5: dff port map( m(0), clk, clrn, prn, q(0) );
	w6: dff port map( m(1), clk, clrn, prn, q(1) );
	w7: dff port map( m(2), clk, clrn, prn, q(2) );

	y(0) <= q(0);
	y(1) <= q(1);
	y(2) <= q(2);
end main;